Regviz

Renesas Electronics /R7FA6M1AD /SDHI0 /SD_STOP

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SD_STOP

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Renesas Electronics/R7FA6M1AD/SDHI0/SD_STOP#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (STP)STP 0Reserved0 (0)SEC 0Reserved

SEC=0

Description

Data Stop Register

Fields

STP

Stop

  • When STP is set to 1 during multiple block transfer, CMD12 is issued to halt the transfer through the SD host interface. However, if a command sequence is halted because of a communications error or timeout, CMD12 is not issued. Although continued buffer access is possible even after STP has been set to 1, the buffer access error bit (ERR5 or ERR4) in SD_INFO2 will be set accordingly.
  • When STP has been set to 1 during transfer for single block write, the access end flag is set when SD_BUF becomes empty, and CMD12 is not issued. If SD_BUF does contain data, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.
  • When STP has been set to 1 during transfer for single block read, the access end flag is set immediately after setting of the STP bit and CMD12 is not issued.
  • When STP is set to 1 during reception of the busy state after an R1b response, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.
  • When STP is set to 1 after a command sequence has been completed, CMD12 is not issued and the access end flag is not set.
  • Set STP to 1 after the response end flag has been set.
  • Set STP to 0 after the response end flag has been set.
Reserved

These bits are read as 0000000. The write value should be 0000000.
SEC

Block Count Enable Set SEC to 1 at multiple block transfer. When SD_CMD is set as follows to start the command sequence while SEC is set to 1, CMD12 is automatically issued to stop multi-block transfer with the number of blocks which is set to SD_SECCNT.

  1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] = 000)
  2. SD_CMD[15:13] = 001 in extended mode (CMD12 is automatically issued, multiple block transfer) When the command sequence is halted because of a communications error or timeout, CMD12 is not automatically issued. NOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1.

0 (0): Disables SD_SECCNT setting value.

1 (1): Enables SD_SECCNT setting value.
Reserved

These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data